
circure-queue-string:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400628 <_init>:
  400628:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40062c:	910003fd 	mov	x29, sp
  400630:	9400004a 	bl	400758 <call_weak_fn>
  400634:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400638:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400640 <.plt>:
  400640:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400644:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0x1011c>
  400648:	f947fe11 	ldr	x17, [x16, #4088]
  40064c:	913fe210 	add	x16, x16, #0xff8
  400650:	d61f0220 	br	x17
  400654:	d503201f 	nop
  400658:	d503201f 	nop
  40065c:	d503201f 	nop

0000000000400660 <memcpy@plt>:
  400660:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  400664:	f9400211 	ldr	x17, [x16]
  400668:	91000210 	add	x16, x16, #0x0
  40066c:	d61f0220 	br	x17

0000000000400670 <strlen@plt>:
  400670:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  400674:	f9400611 	ldr	x17, [x16, #8]
  400678:	91002210 	add	x16, x16, #0x8
  40067c:	d61f0220 	br	x17

0000000000400680 <exit@plt>:
  400680:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  400684:	f9400a11 	ldr	x17, [x16, #16]
  400688:	91004210 	add	x16, x16, #0x10
  40068c:	d61f0220 	br	x17

0000000000400690 <malloc@plt>:
  400690:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  400694:	f9400e11 	ldr	x17, [x16, #24]
  400698:	91006210 	add	x16, x16, #0x18
  40069c:	d61f0220 	br	x17

00000000004006a0 <__libc_start_main@plt>:
  4006a0:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  4006a4:	f9401211 	ldr	x17, [x16, #32]
  4006a8:	91008210 	add	x16, x16, #0x20
  4006ac:	d61f0220 	br	x17

00000000004006b0 <memset@plt>:
  4006b0:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  4006b4:	f9401611 	ldr	x17, [x16, #40]
  4006b8:	9100a210 	add	x16, x16, #0x28
  4006bc:	d61f0220 	br	x17

00000000004006c0 <__gmon_start__@plt>:
  4006c0:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  4006c4:	f9401a11 	ldr	x17, [x16, #48]
  4006c8:	9100c210 	add	x16, x16, #0x30
  4006cc:	d61f0220 	br	x17

00000000004006d0 <abort@plt>:
  4006d0:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  4006d4:	f9401e11 	ldr	x17, [x16, #56]
  4006d8:	9100e210 	add	x16, x16, #0x38
  4006dc:	d61f0220 	br	x17

00000000004006e0 <puts@plt>:
  4006e0:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  4006e4:	f9402211 	ldr	x17, [x16, #64]
  4006e8:	91010210 	add	x16, x16, #0x40
  4006ec:	d61f0220 	br	x17

00000000004006f0 <free@plt>:
  4006f0:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  4006f4:	f9402611 	ldr	x17, [x16, #72]
  4006f8:	91012210 	add	x16, x16, #0x48
  4006fc:	d61f0220 	br	x17

0000000000400700 <printf@plt>:
  400700:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  400704:	f9402a11 	ldr	x17, [x16, #80]
  400708:	91014210 	add	x16, x16, #0x50
  40070c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400710 <_start>:
  400710:	d280001d 	mov	x29, #0x0                   	// #0
  400714:	d280001e 	mov	x30, #0x0                   	// #0
  400718:	aa0003e5 	mov	x5, x0
  40071c:	f94003e1 	ldr	x1, [sp]
  400720:	910023e2 	add	x2, sp, #0x8
  400724:	910003e6 	mov	x6, sp
  400728:	580000c0 	ldr	x0, 400740 <_start+0x30>
  40072c:	580000e3 	ldr	x3, 400748 <_start+0x38>
  400730:	58000104 	ldr	x4, 400750 <_start+0x40>
  400734:	97ffffdb 	bl	4006a0 <__libc_start_main@plt>
  400738:	97ffffe6 	bl	4006d0 <abort@plt>
  40073c:	00000000 	.inst	0x00000000 ; undefined
  400740:	00400c4c 	.word	0x00400c4c
  400744:	00000000 	.word	0x00000000
  400748:	00400d28 	.word	0x00400d28
  40074c:	00000000 	.word	0x00000000
  400750:	00400da8 	.word	0x00400da8
  400754:	00000000 	.word	0x00000000

0000000000400758 <call_weak_fn>:
  400758:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0x1011c>
  40075c:	f947f000 	ldr	x0, [x0, #4064]
  400760:	b4000040 	cbz	x0, 400768 <call_weak_fn+0x10>
  400764:	17ffffd7 	b	4006c0 <__gmon_start__@plt>
  400768:	d65f03c0 	ret
  40076c:	00000000 	.inst	0x00000000 ; undefined

0000000000400770 <deregister_tm_clones>:
  400770:	d0000080 	adrp	x0, 412000 <memcpy@GLIBC_2.17>
  400774:	9101a000 	add	x0, x0, #0x68
  400778:	d0000081 	adrp	x1, 412000 <memcpy@GLIBC_2.17>
  40077c:	9101a021 	add	x1, x1, #0x68
  400780:	eb00003f 	cmp	x1, x0
  400784:	540000a0 	b.eq	400798 <deregister_tm_clones+0x28>  // b.none
  400788:	90000001 	adrp	x1, 400000 <_init-0x628>
  40078c:	f946e421 	ldr	x1, [x1, #3528]
  400790:	b4000041 	cbz	x1, 400798 <deregister_tm_clones+0x28>
  400794:	d61f0020 	br	x1
  400798:	d65f03c0 	ret
  40079c:	d503201f 	nop

00000000004007a0 <register_tm_clones>:
  4007a0:	d0000080 	adrp	x0, 412000 <memcpy@GLIBC_2.17>
  4007a4:	9101a000 	add	x0, x0, #0x68
  4007a8:	d0000081 	adrp	x1, 412000 <memcpy@GLIBC_2.17>
  4007ac:	9101a021 	add	x1, x1, #0x68
  4007b0:	cb000021 	sub	x1, x1, x0
  4007b4:	9343fc21 	asr	x1, x1, #3
  4007b8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4007bc:	9341fc21 	asr	x1, x1, #1
  4007c0:	b40000a1 	cbz	x1, 4007d4 <register_tm_clones+0x34>
  4007c4:	90000002 	adrp	x2, 400000 <_init-0x628>
  4007c8:	f946e842 	ldr	x2, [x2, #3536]
  4007cc:	b4000042 	cbz	x2, 4007d4 <register_tm_clones+0x34>
  4007d0:	d61f0040 	br	x2
  4007d4:	d65f03c0 	ret

00000000004007d8 <__do_global_dtors_aux>:
  4007d8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4007dc:	910003fd 	mov	x29, sp
  4007e0:	f9000bf3 	str	x19, [sp, #16]
  4007e4:	d0000093 	adrp	x19, 412000 <memcpy@GLIBC_2.17>
  4007e8:	3941a260 	ldrb	w0, [x19, #104]
  4007ec:	35000080 	cbnz	w0, 4007fc <__do_global_dtors_aux+0x24>
  4007f0:	97ffffe0 	bl	400770 <deregister_tm_clones>
  4007f4:	52800020 	mov	w0, #0x1                   	// #1
  4007f8:	3901a260 	strb	w0, [x19, #104]
  4007fc:	f9400bf3 	ldr	x19, [sp, #16]
  400800:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400804:	d65f03c0 	ret

0000000000400808 <frame_dummy>:
  400808:	17ffffe6 	b	4007a0 <register_tm_clones>

000000000040080c <init>:
  40080c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400810:	910003fd 	mov	x29, sp
  400814:	f9000fa0 	str	x0, [x29, #24]
  400818:	b90017a1 	str	w1, [x29, #20]
  40081c:	b9002fbf 	str	wzr, [x29, #44]
  400820:	b98017a0 	ldrsw	x0, [x29, #20]
  400824:	d375d000 	lsl	x0, x0, #11
  400828:	97ffff9a 	bl	400690 <malloc@plt>
  40082c:	aa0003e1 	mov	x1, x0
  400830:	f9400fa0 	ldr	x0, [x29, #24]
  400834:	f9000001 	str	x1, [x0]
  400838:	f9400fa0 	ldr	x0, [x29, #24]
  40083c:	f9400000 	ldr	x0, [x0]
  400840:	f100001f 	cmp	x0, #0x0
  400844:	540000c1 	b.ne	40085c <init+0x50>  // b.any
  400848:	90000000 	adrp	x0, 400000 <_init-0x628>
  40084c:	91376000 	add	x0, x0, #0xdd8
  400850:	97ffffa4 	bl	4006e0 <puts@plt>
  400854:	52800000 	mov	w0, #0x0                   	// #0
  400858:	97ffff8a 	bl	400680 <exit@plt>
  40085c:	b9002fbf 	str	wzr, [x29, #44]
  400860:	1400000c 	b	400890 <init+0x84>
  400864:	f9400fa0 	ldr	x0, [x29, #24]
  400868:	f9400001 	ldr	x1, [x0]
  40086c:	b9802fa0 	ldrsw	x0, [x29, #44]
  400870:	d375d000 	lsl	x0, x0, #11
  400874:	8b000020 	add	x0, x1, x0
  400878:	d2810002 	mov	x2, #0x800                 	// #2048
  40087c:	52800001 	mov	w1, #0x0                   	// #0
  400880:	97ffff8c 	bl	4006b0 <memset@plt>
  400884:	b9402fa0 	ldr	w0, [x29, #44]
  400888:	11000400 	add	w0, w0, #0x1
  40088c:	b9002fa0 	str	w0, [x29, #44]
  400890:	b9402fa1 	ldr	w1, [x29, #44]
  400894:	b94017a0 	ldr	w0, [x29, #20]
  400898:	6b00003f 	cmp	w1, w0
  40089c:	54fffe4b 	b.lt	400864 <init+0x58>  // b.tstop
  4008a0:	f9400fa0 	ldr	x0, [x29, #24]
  4008a4:	b94017a1 	ldr	w1, [x29, #20]
  4008a8:	b9001001 	str	w1, [x0, #16]
  4008ac:	f9400fa0 	ldr	x0, [x29, #24]
  4008b0:	b9000c1f 	str	wzr, [x0, #12]
  4008b4:	f9400fa0 	ldr	x0, [x29, #24]
  4008b8:	b9400c01 	ldr	w1, [x0, #12]
  4008bc:	f9400fa0 	ldr	x0, [x29, #24]
  4008c0:	b9000801 	str	w1, [x0, #8]
  4008c4:	f9400fa0 	ldr	x0, [x29, #24]
  4008c8:	b900141f 	str	wzr, [x0, #20]
  4008cc:	d503201f 	nop
  4008d0:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4008d4:	d65f03c0 	ret

00000000004008d8 <empty>:
  4008d8:	d10043ff 	sub	sp, sp, #0x10
  4008dc:	f90007e0 	str	x0, [sp, #8]
  4008e0:	f94007e0 	ldr	x0, [sp, #8]
  4008e4:	b9400801 	ldr	w1, [x0, #8]
  4008e8:	f94007e0 	ldr	x0, [sp, #8]
  4008ec:	b9400c00 	ldr	w0, [x0, #12]
  4008f0:	6b00003f 	cmp	w1, w0
  4008f4:	54000061 	b.ne	400900 <empty+0x28>  // b.any
  4008f8:	52800020 	mov	w0, #0x1                   	// #1
  4008fc:	14000002 	b	400904 <empty+0x2c>
  400900:	52800000 	mov	w0, #0x0                   	// #0
  400904:	910043ff 	add	sp, sp, #0x10
  400908:	d65f03c0 	ret

000000000040090c <full>:
  40090c:	d10043ff 	sub	sp, sp, #0x10
  400910:	f90007e0 	str	x0, [sp, #8]
  400914:	f94007e0 	ldr	x0, [sp, #8]
  400918:	b9400802 	ldr	w2, [x0, #8]
  40091c:	f94007e0 	ldr	x0, [sp, #8]
  400920:	b9400c00 	ldr	w0, [x0, #12]
  400924:	11000400 	add	w0, w0, #0x1
  400928:	f94007e1 	ldr	x1, [sp, #8]
  40092c:	b9401021 	ldr	w1, [x1, #16]
  400930:	1ac10c03 	sdiv	w3, w0, w1
  400934:	1b017c61 	mul	w1, w3, w1
  400938:	4b010000 	sub	w0, w0, w1
  40093c:	6b00005f 	cmp	w2, w0
  400940:	54000061 	b.ne	40094c <full+0x40>  // b.any
  400944:	52800020 	mov	w0, #0x1                   	// #1
  400948:	14000002 	b	400950 <full+0x44>
  40094c:	52800000 	mov	w0, #0x0                   	// #0
  400950:	910043ff 	add	sp, sp, #0x10
  400954:	d65f03c0 	ret

0000000000400958 <enqueue>:
  400958:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  40095c:	910003fd 	mov	x29, sp
  400960:	f9000bf3 	str	x19, [sp, #16]
  400964:	f90017a0 	str	x0, [x29, #40]
  400968:	f90013a1 	str	x1, [x29, #32]
  40096c:	f94017a0 	ldr	x0, [x29, #40]
  400970:	97ffffe7 	bl	40090c <full>
  400974:	7100001f 	cmp	w0, #0x0
  400978:	540000a0 	b.eq	40098c <enqueue+0x34>  // b.none
  40097c:	90000000 	adrp	x0, 400000 <_init-0x628>
  400980:	9137c000 	add	x0, x0, #0xdf0
  400984:	97ffff57 	bl	4006e0 <puts@plt>
  400988:	1400001e 	b	400a00 <enqueue+0xa8>
  40098c:	f94017a0 	ldr	x0, [x29, #40]
  400990:	f9400001 	ldr	x1, [x0]
  400994:	f94017a0 	ldr	x0, [x29, #40]
  400998:	b9400c00 	ldr	w0, [x0, #12]
  40099c:	93407c00 	sxtw	x0, w0
  4009a0:	d375d000 	lsl	x0, x0, #11
  4009a4:	8b000020 	add	x0, x1, x0
  4009a8:	aa0003f3 	mov	x19, x0
  4009ac:	f94013a0 	ldr	x0, [x29, #32]
  4009b0:	97ffff30 	bl	400670 <strlen@plt>
  4009b4:	aa0003e2 	mov	x2, x0
  4009b8:	f94013a1 	ldr	x1, [x29, #32]
  4009bc:	aa1303e0 	mov	x0, x19
  4009c0:	97ffff28 	bl	400660 <memcpy@plt>
  4009c4:	f94017a0 	ldr	x0, [x29, #40]
  4009c8:	b9400c00 	ldr	w0, [x0, #12]
  4009cc:	11000400 	add	w0, w0, #0x1
  4009d0:	f94017a1 	ldr	x1, [x29, #40]
  4009d4:	b9401021 	ldr	w1, [x1, #16]
  4009d8:	1ac10c02 	sdiv	w2, w0, w1
  4009dc:	1b017c41 	mul	w1, w2, w1
  4009e0:	4b010001 	sub	w1, w0, w1
  4009e4:	f94017a0 	ldr	x0, [x29, #40]
  4009e8:	b9000c01 	str	w1, [x0, #12]
  4009ec:	f94017a0 	ldr	x0, [x29, #40]
  4009f0:	b9401400 	ldr	w0, [x0, #20]
  4009f4:	11000401 	add	w1, w0, #0x1
  4009f8:	f94017a0 	ldr	x0, [x29, #40]
  4009fc:	b9001401 	str	w1, [x0, #20]
  400a00:	f9400bf3 	ldr	x19, [sp, #16]
  400a04:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400a08:	d65f03c0 	ret

0000000000400a0c <dequeue>:
  400a0c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400a10:	910003fd 	mov	x29, sp
  400a14:	f9000fa0 	str	x0, [x29, #24]
  400a18:	f9000ba1 	str	x1, [x29, #16]
  400a1c:	b9002fbf 	str	wzr, [x29, #44]
  400a20:	f9400fa0 	ldr	x0, [x29, #24]
  400a24:	97ffffad 	bl	4008d8 <empty>
  400a28:	7100001f 	cmp	w0, #0x0
  400a2c:	540000a0 	b.eq	400a40 <dequeue+0x34>  // b.none
  400a30:	90000000 	adrp	x0, 400000 <_init-0x628>
  400a34:	91380000 	add	x0, x0, #0xe00
  400a38:	97ffff2a 	bl	4006e0 <puts@plt>
  400a3c:	1400002f 	b	400af8 <dequeue+0xec>
  400a40:	f9400fa0 	ldr	x0, [x29, #24]
  400a44:	f9400001 	ldr	x1, [x0]
  400a48:	f9400fa0 	ldr	x0, [x29, #24]
  400a4c:	b9400800 	ldr	w0, [x0, #8]
  400a50:	93407c00 	sxtw	x0, w0
  400a54:	d375d000 	lsl	x0, x0, #11
  400a58:	8b000020 	add	x0, x1, x0
  400a5c:	97ffff05 	bl	400670 <strlen@plt>
  400a60:	b9002fa0 	str	w0, [x29, #44]
  400a64:	f9400fa0 	ldr	x0, [x29, #24]
  400a68:	f9400001 	ldr	x1, [x0]
  400a6c:	f9400fa0 	ldr	x0, [x29, #24]
  400a70:	b9400800 	ldr	w0, [x0, #8]
  400a74:	93407c00 	sxtw	x0, w0
  400a78:	d375d000 	lsl	x0, x0, #11
  400a7c:	8b000020 	add	x0, x1, x0
  400a80:	aa0003e1 	mov	x1, x0
  400a84:	b9802fa0 	ldrsw	x0, [x29, #44]
  400a88:	aa0003e2 	mov	x2, x0
  400a8c:	f9400ba0 	ldr	x0, [x29, #16]
  400a90:	97fffef4 	bl	400660 <memcpy@plt>
  400a94:	f9400fa0 	ldr	x0, [x29, #24]
  400a98:	f9400001 	ldr	x1, [x0]
  400a9c:	f9400fa0 	ldr	x0, [x29, #24]
  400aa0:	b9400800 	ldr	w0, [x0, #8]
  400aa4:	93407c00 	sxtw	x0, w0
  400aa8:	d375d000 	lsl	x0, x0, #11
  400aac:	8b000020 	add	x0, x1, x0
  400ab0:	d2810002 	mov	x2, #0x800                 	// #2048
  400ab4:	52800001 	mov	w1, #0x0                   	// #0
  400ab8:	97fffefe 	bl	4006b0 <memset@plt>
  400abc:	f9400fa0 	ldr	x0, [x29, #24]
  400ac0:	b9400800 	ldr	w0, [x0, #8]
  400ac4:	11000400 	add	w0, w0, #0x1
  400ac8:	f9400fa1 	ldr	x1, [x29, #24]
  400acc:	b9401021 	ldr	w1, [x1, #16]
  400ad0:	1ac10c02 	sdiv	w2, w0, w1
  400ad4:	1b017c41 	mul	w1, w2, w1
  400ad8:	4b010001 	sub	w1, w0, w1
  400adc:	f9400fa0 	ldr	x0, [x29, #24]
  400ae0:	b9000801 	str	w1, [x0, #8]
  400ae4:	f9400fa0 	ldr	x0, [x29, #24]
  400ae8:	b9401400 	ldr	w0, [x0, #20]
  400aec:	51000401 	sub	w1, w0, #0x1
  400af0:	f9400fa0 	ldr	x0, [x29, #24]
  400af4:	b9001401 	str	w1, [x0, #20]
  400af8:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400afc:	d65f03c0 	ret

0000000000400b00 <display>:
  400b00:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400b04:	910003fd 	mov	x29, sp
  400b08:	f9000fa0 	str	x0, [x29, #24]
  400b0c:	90000000 	adrp	x0, 400000 <_init-0x628>
  400b10:	91384000 	add	x0, x0, #0xe10
  400b14:	97fffef3 	bl	4006e0 <puts@plt>
  400b18:	f9400fa0 	ldr	x0, [x29, #24]
  400b1c:	b9400800 	ldr	w0, [x0, #8]
  400b20:	b9002fa0 	str	w0, [x29, #44]
  400b24:	1400000f 	b	400b60 <display+0x60>
  400b28:	f9400fa0 	ldr	x0, [x29, #24]
  400b2c:	f9400001 	ldr	x1, [x0]
  400b30:	b9802fa0 	ldrsw	x0, [x29, #44]
  400b34:	d375d000 	lsl	x0, x0, #11
  400b38:	8b000020 	add	x0, x1, x0
  400b3c:	aa0003e1 	mov	x1, x0
  400b40:	90000000 	adrp	x0, 400000 <_init-0x628>
  400b44:	9138e000 	add	x0, x0, #0xe38
  400b48:	aa0103e2 	mov	x2, x1
  400b4c:	b9402fa1 	ldr	w1, [x29, #44]
  400b50:	97fffeec 	bl	400700 <printf@plt>
  400b54:	b9402fa0 	ldr	w0, [x29, #44]
  400b58:	11000400 	add	w0, w0, #0x1
  400b5c:	b9002fa0 	str	w0, [x29, #44]
  400b60:	f9400fa0 	ldr	x0, [x29, #24]
  400b64:	b9401000 	ldr	w0, [x0, #16]
  400b68:	b9402fa1 	ldr	w1, [x29, #44]
  400b6c:	6b00003f 	cmp	w1, w0
  400b70:	54fffdcb 	b.lt	400b28 <display+0x28>  // b.tstop
  400b74:	d503201f 	nop
  400b78:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400b7c:	d65f03c0 	ret

0000000000400b80 <display_all>:
  400b80:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400b84:	910003fd 	mov	x29, sp
  400b88:	f9000fa0 	str	x0, [x29, #24]
  400b8c:	90000000 	adrp	x0, 400000 <_init-0x628>
  400b90:	91394000 	add	x0, x0, #0xe50
  400b94:	97fffed3 	bl	4006e0 <puts@plt>
  400b98:	b9002fbf 	str	wzr, [x29, #44]
  400b9c:	1400000f 	b	400bd8 <display_all+0x58>
  400ba0:	f9400fa0 	ldr	x0, [x29, #24]
  400ba4:	f9400001 	ldr	x1, [x0]
  400ba8:	b9802fa0 	ldrsw	x0, [x29, #44]
  400bac:	d375d000 	lsl	x0, x0, #11
  400bb0:	8b000020 	add	x0, x1, x0
  400bb4:	aa0003e1 	mov	x1, x0
  400bb8:	90000000 	adrp	x0, 400000 <_init-0x628>
  400bbc:	9139e000 	add	x0, x0, #0xe78
  400bc0:	aa0103e2 	mov	x2, x1
  400bc4:	b9402fa1 	ldr	w1, [x29, #44]
  400bc8:	97fffece 	bl	400700 <printf@plt>
  400bcc:	b9402fa0 	ldr	w0, [x29, #44]
  400bd0:	11000400 	add	w0, w0, #0x1
  400bd4:	b9002fa0 	str	w0, [x29, #44]
  400bd8:	f9400fa0 	ldr	x0, [x29, #24]
  400bdc:	b9401000 	ldr	w0, [x0, #16]
  400be0:	b9402fa1 	ldr	w1, [x29, #44]
  400be4:	6b00003f 	cmp	w1, w0
  400be8:	54fffdcb 	b.lt	400ba0 <display_all+0x20>  // b.tstop
  400bec:	d503201f 	nop
  400bf0:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400bf4:	d65f03c0 	ret

0000000000400bf8 <clean>:
  400bf8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400bfc:	910003fd 	mov	x29, sp
  400c00:	f9000fa0 	str	x0, [x29, #24]
  400c04:	f9400fa0 	ldr	x0, [x29, #24]
  400c08:	f9400000 	ldr	x0, [x0]
  400c0c:	f100001f 	cmp	x0, #0x0
  400c10:	54000180 	b.eq	400c40 <clean+0x48>  // b.none
  400c14:	f9400fa0 	ldr	x0, [x29, #24]
  400c18:	f9400000 	ldr	x0, [x0]
  400c1c:	97fffeb5 	bl	4006f0 <free@plt>
  400c20:	f9400fa0 	ldr	x0, [x29, #24]
  400c24:	f900001f 	str	xzr, [x0]
  400c28:	f9400fa0 	ldr	x0, [x29, #24]
  400c2c:	b900081f 	str	wzr, [x0, #8]
  400c30:	f9400fa0 	ldr	x0, [x29, #24]
  400c34:	b9000c1f 	str	wzr, [x0, #12]
  400c38:	f9400fa0 	ldr	x0, [x29, #24]
  400c3c:	b900101f 	str	wzr, [x0, #16]
  400c40:	d503201f 	nop
  400c44:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400c48:	d65f03c0 	ret

0000000000400c4c <main>:
  400c4c:	d12143ff 	sub	sp, sp, #0x850
  400c50:	a9007bfd 	stp	x29, x30, [sp]
  400c54:	910003fd 	mov	x29, sp
  400c58:	90000000 	adrp	x0, 400000 <_init-0x628>
  400c5c:	913a4000 	add	x0, x0, #0xe90
  400c60:	f90427a0 	str	x0, [x29, #2120]
  400c64:	90000000 	adrp	x0, 400000 <_init-0x628>
  400c68:	913a8000 	add	x0, x0, #0xea0
  400c6c:	f90423a0 	str	x0, [x29, #2112]
  400c70:	90000000 	adrp	x0, 400000 <_init-0x628>
  400c74:	913ac000 	add	x0, x0, #0xeb0
  400c78:	f9041fa0 	str	x0, [x29, #2104]
  400c7c:	90000000 	adrp	x0, 400000 <_init-0x628>
  400c80:	913b0000 	add	x0, x0, #0xec0
  400c84:	f9041ba0 	str	x0, [x29, #2096]
  400c88:	910043a0 	add	x0, x29, #0x10
  400c8c:	d2810001 	mov	x1, #0x800                 	// #2048
  400c90:	aa0103e2 	mov	x2, x1
  400c94:	52800001 	mov	w1, #0x0                   	// #0
  400c98:	97fffe86 	bl	4006b0 <memset@plt>
  400c9c:	52800140 	mov	w0, #0xa                   	// #10
  400ca0:	b9082fa0 	str	w0, [x29, #2092]
  400ca4:	912043a0 	add	x0, x29, #0x810
  400ca8:	b9482fa1 	ldr	w1, [x29, #2092]
  400cac:	97fffed8 	bl	40080c <init>
  400cb0:	912043a0 	add	x0, x29, #0x810
  400cb4:	f94427a1 	ldr	x1, [x29, #2120]
  400cb8:	97ffff28 	bl	400958 <enqueue>
  400cbc:	912043a0 	add	x0, x29, #0x810
  400cc0:	f94423a1 	ldr	x1, [x29, #2112]
  400cc4:	97ffff25 	bl	400958 <enqueue>
  400cc8:	912043a0 	add	x0, x29, #0x810
  400ccc:	f9441fa1 	ldr	x1, [x29, #2104]
  400cd0:	97ffff22 	bl	400958 <enqueue>
  400cd4:	912043a0 	add	x0, x29, #0x810
  400cd8:	f9441ba1 	ldr	x1, [x29, #2096]
  400cdc:	97ffff1f 	bl	400958 <enqueue>
  400ce0:	912043a0 	add	x0, x29, #0x810
  400ce4:	97ffff87 	bl	400b00 <display>
  400ce8:	910043a1 	add	x1, x29, #0x10
  400cec:	912043a0 	add	x0, x29, #0x810
  400cf0:	97ffff47 	bl	400a0c <dequeue>
  400cf4:	912043a0 	add	x0, x29, #0x810
  400cf8:	97ffffa2 	bl	400b80 <display_all>
  400cfc:	910043a1 	add	x1, x29, #0x10
  400d00:	90000000 	adrp	x0, 400000 <_init-0x628>
  400d04:	913b4000 	add	x0, x0, #0xed0
  400d08:	97fffe7e 	bl	400700 <printf@plt>
  400d0c:	912043a0 	add	x0, x29, #0x810
  400d10:	97ffffba 	bl	400bf8 <clean>
  400d14:	52800000 	mov	w0, #0x0                   	// #0
  400d18:	a9407bfd 	ldp	x29, x30, [sp]
  400d1c:	912143ff 	add	sp, sp, #0x850
  400d20:	d65f03c0 	ret
  400d24:	00000000 	.inst	0x00000000 ; undefined

0000000000400d28 <__libc_csu_init>:
  400d28:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400d2c:	910003fd 	mov	x29, sp
  400d30:	a901d7f4 	stp	x20, x21, [sp, #24]
  400d34:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0x1011c>
  400d38:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0x1011c>
  400d3c:	91374294 	add	x20, x20, #0xdd0
  400d40:	913722b5 	add	x21, x21, #0xdc8
  400d44:	a902dff6 	stp	x22, x23, [sp, #40]
  400d48:	cb150294 	sub	x20, x20, x21
  400d4c:	f9001ff8 	str	x24, [sp, #56]
  400d50:	2a0003f6 	mov	w22, w0
  400d54:	aa0103f7 	mov	x23, x1
  400d58:	9343fe94 	asr	x20, x20, #3
  400d5c:	aa0203f8 	mov	x24, x2
  400d60:	97fffe32 	bl	400628 <_init>
  400d64:	b4000194 	cbz	x20, 400d94 <__libc_csu_init+0x6c>
  400d68:	f9000bb3 	str	x19, [x29, #16]
  400d6c:	d2800013 	mov	x19, #0x0                   	// #0
  400d70:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400d74:	aa1803e2 	mov	x2, x24
  400d78:	aa1703e1 	mov	x1, x23
  400d7c:	2a1603e0 	mov	w0, w22
  400d80:	91000673 	add	x19, x19, #0x1
  400d84:	d63f0060 	blr	x3
  400d88:	eb13029f 	cmp	x20, x19
  400d8c:	54ffff21 	b.ne	400d70 <__libc_csu_init+0x48>  // b.any
  400d90:	f9400bb3 	ldr	x19, [x29, #16]
  400d94:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400d98:	a942dff6 	ldp	x22, x23, [sp, #40]
  400d9c:	f9401ff8 	ldr	x24, [sp, #56]
  400da0:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400da4:	d65f03c0 	ret

0000000000400da8 <__libc_csu_fini>:
  400da8:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400dac <_fini>:
  400dac:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400db0:	910003fd 	mov	x29, sp
  400db4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400db8:	d65f03c0 	ret
